(1) Field of the Invention
The invention relates to an electrically erasable programmable read only memory (EEPROM) and a method for producing the EEPROM, and more particularly to the EEPROM that is formed on a substrate.
(2) Description of the Related Art
An electrically erasable programmable read only memory (EEPROM), widely seen in various electronic products, is characterized in is capability of storing data under a no-source environment, fast accessing, larger capacity, and a small size.
Referring to FIG. 1, an EEPROM structure disclosed in U.S. Pat. No. 5,998,830 is schematically shown. The EEPROM 1 as shown is a single-poly silicon formed on insulator (SOI) structure.
The single-poly silicon EEPROM 1 mainly uses two neighboring metal oxide semiconductors (MOS), the first MOS 11 and the second MOS 12, as the memory cells. To avoid possible “latch up” between the first MOS 11 and the second MOS 12, the MOSes 11 and 12 are then form on a SOI 13. As shown, the SOI 13, formed on a silicon substrate 14, includes an insulator layer 131, generally a silicon oxide, and a silicon layer 132. The silicon layer 132 is isolated from the silicon substrate 141 by the insulator layer 131.
As shown in FIG. 1, each of the MOSes 11 and 12 has a gate 110 or 120, a drain 111 or 121, a source 112 or 122, respectively. The drain 111 of the first MOS 11 is electrically connected with a bit line VD, the source 112 is connected to grounded Vs, and the gate 110 as a floating gate of the EEPROM 1 is electrically connected to the gate 120 of the second MOS 12. The drain 121 and the source 122 of the second MOS 12 are coupled to a control gate of the EEPROM 1 for receiving a control voltage Vg.
In operating the EEPROM 1, different control voltages Vg are utilized to determine the “tunneling” of thermal electrons to the floating gate. In the case that electrons enter the floating gate, the memory cell of the EEPROM 1 will be set at a value “1”. On the other hand, in the case that the electrons escape from the floating gate, the memory cell of the EEPROM 1 will be set at a value “0”. Without altering the control voltage Vg, the information or data stored into the memory cell will be maintained even that no power is present.
Though the EEPROM 1 has many advantages as described above and is also widely accepted in various electronic products, yet current application that the electric connection between the glass substrate 2 and the EEPROM 1 via the flexible printed circuit board 22 requires the EEPROM 1 to be mounted on a printed circuit board 21 in advance, as shown in FIG. 2. For the EEPROM 1 is formed exterior to the glass substrate 2, packing cost to include the EEPROM 1 and the flexible printed circuit board 21 would be increased and also the whole package including the glass substrate 2 would be big and thick.
It is noted that the improvement to form the EEPROM directly onto the glass substrate can reduce the packing cost of the EEPROM, waive the flexible printed circuit board, thus increase the speed of data accessing, and reduce the reaction time of image processing.